1. Field of the Invention
The present invention relates to a detector detecting plasma-induced damage to gate insulating films in MOS structures during the semiconductor fabrication process, and it also relates to a damage evaluation method.
2. Description of the Background Art
A recent trend toward higher-density semiconductor devices has been increasing the use of high damage processes in the fabrication of semiconductor devices. Especially plasma processes using high-energy charges have a great impact on semiconductor devices. Thus, recent studies have been directed toward damage-reduced plasma processes. At the same time, the need for a high-sensitivity plasma-induced damage detector and a method for making a low-cost, high-precision, short-time damage detection have arisen.
One of the problems with the plasma-induced impact on semiconductor devices is charging damage to gate insulating films in MOS structures. FIGS. 5 and 6 schematically illustrate this problem.
In FIG. 5, a chamber CB comprises plasma producing mechanisms GN for producing plasma gas PG while holding a wafer WF by a lower electrode (not shown). The plasma gas PG produced in the chamber CB sends charges CH to the wafer WF. The charges CH react with materials on the surface of the wafer WF to apply, for example, etching to the surface. Of the charges CH, some of electrons E1 enter into wiring, etc. formed on the surface of the wafer WF. These electrons E1 either stay in the wafer WF, or return from the wafer WF back to the plasma gas PG, or go through the wafer WF and escape to the ground through the lower electrode (not shown).
FIG. 6 schematically shows a MOS transistor M1 on the surface of the wafer WF in FIG. 5 during a plasma process. The MOS transistor M1 consists of a gate electrode G and a gate insulating film OX formed on the surface of a substrate SUB isolated by element isolation regions IR that are formed by the LOCOS method, etc., and source/drain regions S, D with impurities doped therein. On the upper surface of the gate electrode G, an interlayer insulating film (not shown) is formed and a wire IL2 is formed on top of that. The wire IL2 is connected to the gate electrode G by a contact hole H1 formed in the interlayer insulating film.
On applying a plasma process to such a MOS transistor M1, the charge CH is sent to the vicinity of the wiring IL2 as shown in FIG. 6. Of the charge CH, some of electrons (E11, E12, E13) enter into the wire IL2. Here, these electrons are classified into three groups according to their entering forms, namely, electrons E11 going through the wire IL2 and entering directly into the contact hole H1; electrons E12 entering into the wire IL2 from the side surfaces; and electrons E13 entering into the wire IL2 from the upper surface. The electrons E11, E12, and E13 try to move to the gate electrode G to flow to the substrate SUB. As a higher-density MOS transistor M1 has a thinner gate insulating film OX, the Fowler-Nordheim tunneling current FN caused by the movement of the electrons E11, E12, and E13 flows easily (but arrows in FIG. 6 indicate a flow of electrons). This flow of the tunneling current FN often causes trapping of some of electrons E11, E12, and E13 in the gate insulating film OX, generating defects in the gate insulating film OX. Depending on the degree of defects, dielectric breakdown may be developed.
Such defects are illustrated in FIGS. 7A to 7C. The drawings show a cross section of a MOS transistor M1 consisting of a gate electrode G, a gate insulating film OX, and side walls SW all formed on the P-type substrate SUB, and an N-type source electrode S and an N-type drain electrode D both formed in the substrate SUB. This MOS transistor M1 is of N-channel type. FIG. 7A shows that electrons E1 caused by plasma charging flow from the gate electrode G to the substrate SUB through the gate insulating film OX. FIG. 7B shows that the trapped electrons E1 are annealed out by heat treatment. The defects in the gate insulating film OX will recover by this annealing somewhat but not completely, so that trap levels TL remain. In this state, as shown in FIG. 7C, the source electrode S is grounded to apply voltages Vgs, Vds and Vsub to the gate electrode G, the drain electrode D, and the substrate SUB, respectively. At this time, the electrons E2 that migrate from the source electrode S to the drain electrode D tend to be hot carriers in the vicinity of the drain electrode D. When the hot-carrier electrons E2 collide with atoms in the substrate SUB, producing electron-hole pairs, some of newly produced holes P1 turn to be a substrate current Isub that flows in the direction of the voltage Vsub, and some of newly produced electrons E3 move in the direction of the voltage Vgs to be a gate current Ig. However, the electrons E3 are trapped in the trap levels TL in the gate insulating film OX. That is, an application of electrical stress to the N-channel MOS transistor M1 often causes charge trapping in the gate insulating film OX in a short time. Accordingly, a repetition of such electrical stress accelerates degradation in transistor characteristics.
As a method for evaluating the degradation level of a gate insulating film deteriorated by such plasma damage, there were, for example, the CVS (Constant Voltage Stress) method and the CCS (constant Current Stress) method both utilizing a wafer with a large-area TEG (Test Element Group) having a large number of gate insulating films. The former was a method for evaluating the degradation level by examining degradation with times from the time a constant voltage is applied to a damaged gate insulating film to the time dielectric breakdown of the film occurs. The latter was a method for evaluating the degradation level by examining the amount of charge injected during a period between the application of a constant current to a damaged gate insulating film and the occurrence of dielectric breakdown of the film.
Alternatively, there were also the SPV (Surface Photo Voltage) method for evaluating degradation by measuring surface photoelectromotive force of each element to examine a potential distribution by the use of a wafer with a large-area TEG having a large number of gate insulating films, and then identifying information on the trap levels; and a method for evaluating degradation by calculating the amount of charge injection from current-voltage characteristics, using a wafer with a large-area TEG having a large number of EEPROMs (Electrical Erasable and Programmable ROM).
However, these conventional plasma damage evaluation methods utilized a TEG-equipped wafer dedicated for damage detection, and fabrication of such a dedicated wafer increases manufacturing cost. Such dedicated wafers were also not necessarily fabricated under the same conditions as a product wafer, so that the evaluation thereof would not be identical with that of the product wafer. Further, because of their low damage measuring sensitivity and long measuring time, the methods were not desirable to obtain sufficiently effective data.
As an alternative of these measuring methods, there has been developed a technique for fabricating a TEG for degradation detection of gate insulating films integrally with a product wafer in the fabrication of the product wafer, thereby obtaining the same process conditions as the product wafer and also reducing the manufacturing cost.
The Japanese Patent Laid-Open No. 10-79407A, for example, discloses a device in which through an interlayer insulating film, metal wires are densely formed on a gate electrode of an MOS capacitor formed integrally with a product wafer, and those metal wires are used as high-sensitivity plasma damage antennas; and a method utilizing the device, for evaluating a degradation level by examining the amount of charge injected until the occurrence of dielectric breakdown of insulating films in the MOS capacitor.
Another Japanese Patent Laid-Open No. 7-78829A discloses, as an experimental device for detecting plasma damage with high sensitivity, a plasma damage detector PD2 with a pectinate antenna AT1 shown in FIG. 8 and a plasma damage detector PD3 with a large-area antenna AT2 shown in FIG. 9.
The detector PD2 comprises a similar MOS transistor M1 to that in FIG. 6. More specifically, the MOS transistor M1 consists of the gate insulating film OX and the gate electrode G formed on the surface of the substrate SUB isolated by the element isolation regions IR that are formed by the LOCOS method, etc., and the source/drain regions S, D with carriers injected therein. The pectinate anterna AT1 is then formed in series with the gate electrode G. Having a large antenna circumference, the pectinate antenna AT1 can readily accumulate charges entering from the side surfaces, e.g., the electrons E12 in FIG. 6. In this respect, it is ideal for detecting charging damage by plasma etching with high sensitivity. This is because forming a wiring portion into a pectinate antenna by means of etching causes a reaction in the periphery of the pectinate antenna with resists, which allows easy entrance of the electrons from the side surfaces.
The detector PD3 comprises a similar MOS transistor M1 to that of the detector PD2, in which the large-area antenna AT2 is formed in series with the gate electrode G. The large-area antenna AT2 can readily accumulate charges entering from the upper surface, e.g., the electrons E13 in FIG. 6. In this respect, it is ideal for detecting charging damage by plasma ashing with high sensitivity. This is because ashing causes a reaction on the entire surface of resists formed on the large-area antenna AT2, which allows easy entrance of the electrons from the upper surface.
In both structures of the detectors PD2 and PD3, however, it was difficult to readily accumulate charges entering directly into contact holes between the wire and the gate electrode or into through holes between multilayer interconnections, e.g. the electrons E11 in FIG. 6.
A first aspect of the present invention is directed to a plasma damage detection test structure comprising: a semiconductor substrate having a surface; first and second current electrodes provided apart from each other in the surface of the semiconductor substrate; an insulating film provided on the surface of the semiconductor substrate sandwiched between the first and second current electrodes; a control electrode opposed to the semiconductor substrate with the insulating film therebetween; a first wire connected to the control electrode; a second wire connected to the first wire and located farther from the semiconductor substrate than the first wire; and a plurality of contact or through holes which intervene between the first wire and the second wire and which is located across the first and second wires.
According to a second aspect of the present invention, the plasma damage detection test structure of the first aspect further comprises: a diode whose anode is grounded and whose cathode is connected to the second wire.
A third aspect of the present invention is directed to a plasma damage evaluation method using a plasma damage detection test structure comprising a semiconductor substrate having a surface, first and second current electrodes provided apart from each other in the surface of the semiconductor substrate, an insulating film provided on the surface of the semiconductor substrate sandwiched between the first and second current electrodes, a control electrode opposed to the semiconductor substrate with the insulating film therebetween, a first wire connected to the control electrode, a second wire connected to the first wire and located farther from the semiconductor substrate than the first wire, a plurality of contact or through holes intervening between the first wire and the second wire and located across the first and second wires; and a diode whose anode is grounded and whose cathode is connected to the second wire. The plasma damage evaluation method comprises the steps of: applying a first voltage between the first and second current electrodes; measuring a parameter of the plasma damage detector in applying a second voltage between the control electrode and the second current electrode; and evaluating plasma damage by estimating a value of a hot carrier lifetime from a known correlation between the hot carrier lifetime and the parameter.
A fourth aspect of the present invention is directed to a plasma damage evaluation method comprising the steps of: (a) preparing a semiconductor substrate having a surface; (b) forming a first conductive material on the surface; (c) patterning the first conductive material to form a first wire; (d) forming an interlayer insulating film so as to cover the first wire; (e) forming a plurality of contact or through holes in the interlayer insulating film across the first wire; (f) forming a second conductive material so as to fill the plurality of contact or through holes; and (g) patterning the second conductive material to form a second wire.
The plasma damage detection test structure of the first aspect achieves high-sensitivity detection of damage to the insulating films from the charge entering directly into the contact or through holes during the plasma process.
The plasma damage detection test structure of the second aspect sends the charge entering into the second wire during the plasma process to the ground, excepting the charge entering directly into the contact or through holes between the first and second wires. It thus achieves high-sensitivity detection of damage to the insulating films only from the charge entering directly into the contact or through holes between the first and second wires.
With the plasma damage evaluation method of the third aspect, we can estimate the hot carrier lifetime only by applying the first and second voltages for a short time for the measurement of the parameter value. Accordingly, this method allows a low-cost, high-precision, short-time evaluation of the plasma damage to the insulating films from the charge entering directly into the contact or through holes.
With the plasma damage evaluation method of the fourth aspect, we can readily detect electrons entering into the plurality of contact or through holes when the plasma etch method is applied to the step (e) or (g).
Thus, an objective of the present invention is to achieve an especially high-sensitivity detection test structure that detects the impact of charges entering directly into contact or through holes on gate insulating films, and to obtain a plasma damage evaluation method using the detector.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.